FIG. 1 is a partial top view of a related art dual damascene via interconnect. In FIG. 1, a lower level wire 100 is electrically connected to an upper level wire 105 by a via 110. Lower level wire 100 is comprised of a conductive liner 115 and a core conductor 120. Upper level wire 105 is comprised of a conductive liner 125 and a core conductor 130. Via 105 is integrally formed with upper level wire 105 and comprises conductive liner 125 and core conductor 130. Via 110 is aligned distances “d1” and “d2” from sides 135 of upper wire 105. The two distances, “d1” and “d2” may or may not be equal. Via 110 is aligned with distances “d3” and “d4” from sides 140 of lower wire 100. The two distances, “d3” and “d4” may or may not be equal. The thickness of conductive liner 115 is less than distances “d3” and “d4.” and the thickness of conductive liner 125 is less than distances “d1” and “d2.”
Lower level wire 100 is formed by a damascene process or a dual damascene process. In a damascene process, a trench is formed in a dielectric layer, for example, by reactive ion etching (RIE) of the dielectric layer, and liner and core conductors deposited, filling the trench. The liner is generally deposited conformally as a thin layer, coating the bottom and sides of the trench. The core conductor may be deposited by any suitable method known to the industry, including, but not limited to, physical vapor deposition, chemical vapor deposition and plating, until the trench is filled. A chemical-mechanical-polish process (CMP) is performed to remove excess metal and planarize the top of the metal filled trench with the top surface of the dielectric. Upper level wire 105 and via 110 are formed by a dual-damascene process. In a dual damascene process, a trench for the wire is first etched part way into a dielectric layer. Next via openings are etched in the bottom of the trench through the remaining dielectric to expose an underlying wire or electrical contact to a semiconductor device. Of course, the via openings may be etched first, followed by etching of the trench. Liner and core conductors are then deposited and a CMP process performed as for a damascene process. In a dual damascene process, the liner also coats the sides and bottom of the via openings as well as the bottom and sides of the trench. Lower level wire 100 may be formed by a dual damascene process as well.
FIG. 2A is a partial cross-section view through 2-2 of FIG. 1. In FIG. 2A, a lower dielectric layer 145 is formed on a semiconductor substrate 150. Lower level wire 100 is formed in a lower dielectric layer 145. Formed on top of lower dielectric layer 145 and lower level wire 100 is an upper dielectric layer 155. Upper level wire 105 and via 110 are formed in upper dielectric layer 155. Conductive liner 125 covers a bottom 160 of upper wire 105 and a sidewall 165 and a bottom 170 of via 110. Conductive liner 115 covers sidewall 175 and a bottom 180 of lower level wire 100. Via 105 is embedded a distance “d5” into core conductor 120 of lower level wire 100.
Referring to FIG. 1 and FIG. 2A, a ring 185 of core conductor 120 of lower level wire 100 is in contact with upper dielectric layer 155. Conductive liner 125 is not in electrical contact with conductive liner 115. The electrical path from upper level wire 105 to lower wire 100 consists of core conductor 130 to conductive liner 125 and from the conductive liner to core conductor 120.
In one example, core conductors 120 and 130 are copper and conductive liners 115 and 125 comprise a dual tantalum nitride/tantalum layers (the tantalum nitride being the outer layer.) The tantalum nitride layer acts, as an adhesion layer and as a copper migration barrier, while the tantalum layer is a relatively good conductive layer. In another example, core conductors 120 and 130 are aluminum or aluminum alloys such as aluminum/copper or aluminum/copper/silicon and conductive liners 115 and 125 comprise dual titanium nitride/titanium layers(the titanium nitride being the outer layer) or a tungsten layer. Of course, any of the core conductor materials listed above may be used in combination with any of the conductive liner materials listed above.
A problem with the afore-mentioned copper and aluminum metallurgies is a phenomenon called electro-migration. In electro-migration, core conductor atoms (copper or aluminum) are driven in the direction of electron flow. In the case of a via contacting a lower wire and for electron flow from the via to the lower wire, the core conductor atoms of the lower wire are driven away from the via leaving behind a void.
FIG. 2B is a partial cross-section view through 2-2 of FIG. 1 illustrating electro-migration voiding. In FIG. 2B, a void 190 has been formed by electro-migration. Core conductor 120 is not contacting liner 125 and consequentially, there is no electrical contact between upper level wire 105 (through via 110) and lower wire level 100.
Clearly, in the case of a via contacting a lower wire, the lower wire being wider than the contacting via, the potential for catastrophic open circuit failures exist. To fully realize the full benefit of copper (or aluminum) dual damascene technology a method of ensuring electrical connection between the via and the lower wire even when very large or even catastrophic core conductor voiding occurs is required.